module cla_adder_4 (A, B,CI, SUM, CO);
	input [3:0] A;
	input [3:0] B;
	input CI;
	output [3:0] SUM;
	output CO;
	wire c1, c2, c3;
	wire g0, p0, g1, p1, g2, p2, g3, p3;


//first bit
	assign SUM[0] = A[0]^B[0]^CI;
	assign g0 = A[0]&B[0];
	assign p0 = A[0]^B[0];
	assign c1 = g0 | (p0&CI);

//second bit
        assign SUM[1] = A[1]^B[1]^c1;
	assign g1 = A[1]&B[1];
	assign p1 = A[1]^B[1];
	assign c2 = g1 | (g0&p1) | (CI&p0&p1);

//third bit
	assign SUM[2] = A[2]^B[2]^c2;
	assign g2 = A[2]&B[2];
        assign p2 = A[2]^B[2];
	assign c3 = g2 | (g1&p2) | (g0&p1&p2) | (CI&p0&p1&p2);

//forth bit
	assign SUM[3] = A[3]^B[3]^c3;
	assign g3 = A[3]&B[3];
	assign p3 = A[3]^B[3];
	assign CO = g3 | (g2&p3) | (g1&p2&p3) | (g0&p1&p2&p3) | (CI&p0&p1&p2&p3);

endmodule	


